SHANGHAI, China, May 25, 2026 – Today, at the International Symposium on Circuits and Systems (ISCAS) 2026, hosted by the Institute of Electrical and Electronics Engineers (IEEE), He Tingbo from Huawei delivered a keynote speech titled "Exploring and Practicing New Paths in Semiconductors," in which he introduced a new principle governing the development of the semiconductor industry – Tau's Law. Tau's Law proposes replacing "geometric scaling" with "time (τ) scaling" as a new principle for the development of semiconductors and electronic systems – continuously reducing signal propagation delay and continuously increasing transistor density through innovative technologies such as logic folding, thereby achieving continuous development of semiconductors and electronic systems.

In recent years, Moore's Law, which has dominated the semiconductor industry for over half a century, has faced serious challenges, both in terms of physical limitations and economic efficiency. Due to the slowdown in transistor geometric miniaturization and the declining cost advantages of transistors, overcoming the limitations of traditional process paths and exploring a new, sustainable development path that can meet the exponentially increasing demands for computing power has become a pressing issue for the global semiconductor industry. Tau's Law provides an effective path to address this problem.

Huawei has innovatively proposed key technologies such as "Logic Folding" and created a multi-level collaborative optimization system that encompasses devices, circuits, chips, and systems. This system aims to systematically reduce the time constant τ, leading to continuous improvement in performance, energy efficiency, and transistor density at all levels:

Device Level: By optimizing transistors, interconnect resistances, and parasitic capacitances, the system minimizes the time constant τ at the device level on a physical basis.

Circuit Level: Through logic folding technology, the system breaks through the physical limitations of traditional planar layouts, significantly shortens the length of critical paths, and effectively reduces the resistance and capacitive load of signal propagation, leading to a substantial improvement in transistor density and circuit performance.

Chip Level: Through full-stack hardware-software co-design of "software, architecture, and chip," the system achieves fine-grained control of instruction and data flows based on actual workload, improves parallelism and efficiency at the system level, and significantly reduces execution time.

System Level: The system defines the Lingqu bus, reconstructs the interconnection protocol of computing systems, and achieves unified memory addressing and native memory semantics for supernodes, thereby significantly reducing system communication latency.

In his keynote speech, He Tingbo detailed how Huawei is applying Tau's Law (τ) to the fields of smartphones and artificial intelligence. Over the past six years, Huawei has successfully designed and mass-produced 381 chips based on Tau's Law, which widely cover the needs of various industries. Among them, the Kirin chip, scheduled for release in the fall of 2026, is the first to utilize logic folding technology, which significantly improves performance. It is expected that by 2031, the transistor density in high-end chips based on Tau's Law will reach the same level as 1.4-nanometer processes.

Looking to the future, He Tingbo said: "The future undoubtedly belongs to open collaboration. In the evolution of semiconductors, no single company can address all the important issues on its own. In accordance with Tau's law, we look forward to close collaboration with scientists, engineers, and industry partners around the world to jointly promote the further development of the semiconductor and electronics industries."

huawei.com